#include <hi6220.h>
#include <hisi_ipc.h>
#include <hisi_pwrc.h>
+#include <mmio.h>
#include <platform_def.h>
#include "hikey_def.h"
BL31_COHERENT_RAM_LIMIT);
}
+/* Initialize EDMAC controller with non-secure mode. */
+static void hikey_edma_init(void)
+{
+ int i;
+ uint32_t non_secure;
+
+ non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC;
+ mmio_write_32(EDMAC_SEC_CTRL, non_secure);
+
+ for (i = 0; i < EDMAC_CHANNEL_NUMS; i++) {
+ mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18));
+ }
+}
+
void bl31_platform_setup(void)
{
/* Initialize the GIC driver, cpu and distributor interfaces */
gicv2_pcpu_distif_init();
gicv2_cpuif_enable();
+ hikey_edma_init();
+
hisi_ipc_init();
hisi_pwrc_setup();
}
#define DWUSB_BASE 0xF72C0000
+#define EDMAC_BASE 0xf7370000
+#define EDMAC_SEC_CTRL (EDMAC_BASE + 0x694)
+#define EDMAC_AXI_CONF(x) (EDMAC_BASE + 0x820 + (x << 6))
+#define EDMAC_SEC_CTRL_INTR_SEC (1 << 1)
+#define EDMAC_SEC_CTRL_GLOBAL_SEC (1 << 0)
+#define EDMAC_CHANNEL_NUMS 16
+
#define PMUSSI_BASE 0xF8000000
#define SP804_TIMER0_BASE 0xF8008000